![]() Thus, if a transmission gate has the input signal connected to the NMOS and the complemented input signal connected to the PMOS, it’s an “active high” gate-i.e., it behaves like a closed switch when the input signal is logic high and an open switch when the input signal is logic low. A logic-high signal causes an NMOS to turn on and a PMOS to turn off. First, we need to remember the following: A logic-low signal causes an NMOS (indicated by the absence of a circle adjacent to the gate) to turn off and a PMOS (indicated by the presence of a circle adjacent to the gate) to turn on. One of my textbooks has a PTL implementation that requires eight transistors it consists of two transmission gates and two inverters (one for the A input and one for the B input the inverters are not shown in the diagram). Pass-transistor logic allows us to greatly reduce this transistor count. Creating a two-input XOR truth table using typical CMOS logic is a bit awkward- twelve transistors are required, despite the fact that other standard Boolean functions require only four (NAND, NOR) or six (AND, OR). The XOR function is an example of an application in which PTL really does offer significant benefits. My guess is that IC designers don’t often use PTL for AND gates. Now we need five transistors, versus six for the standard AND gate. Thus, a more respectable PTL AND gate would look like this: A lone NMOS can effectively transfer a logic-low signal from input to output, but it causes serious signal degradation when it attempts to transfer a logic-high signal. However, we’re using NMOS transistors here instead of transmission gates. Now we have an AND gate that requires only two transistors instead of six, if the preceding circuitry happens to provide both $$B$$ and $$\overline$$ is not available from the preceding circuitry, it has to be generated by the PTL AND gate, and that requires another two transistors. If B is low, the upper transistor is in cutoff, but the output is not floating because the lower transistor, which is driven by the complement of B, provides a low-resistance path to ground. If B is high, the output has a low-resistance path to the supply rail or ground, depending on the state of A (we’re assuming here that the A signal is generated by a low-resistance driver of some kind). If we want a PTL circuit that is more consistent with the functionality of the CMOS circuit, we need an additional transistor: However, we can’t directly compare the NMOS-plus-resistor implementation to the CMOS implementation, because the CMOS version always provides a low-resistance output connection whereas the PTL version does not. This certainly is a major reduction in component count compared to the typical CMOS two-input AND gate, which requires six transistors. In the preceding article, we looked at a two-input AND gate consisting of only one transistor and one resistor. The loss in electrical performance is especially disconcerting when the pass/block functionality is provided by an NMOS transistor instead of a CMOS transmission gate (see this article for more information). The bottom line with pass-transistor logic is that you are trading electrical performance for the possibility of reducing transistor count. As the name implies, PTL uses transistors as switches that pass or block a signal this is in contrast to the “typical” CMOS approach whereby an output node is always driven to logic low or logic high via the low-resistance path provided by a PMOS or NMOS transistor. In a previous article, I introduced the concept and basic characteristics of pass-transistor logic (PTL). This article presents efficient, pass-transistor-based implementations of important digital functionality.
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